As is known, a chip scale package (CSP) is a semiconductor package that houses a semiconductor die, where the external dimensions of the semiconductor package approximates the size of the semiconductor die. Some chip scale packages (CSPs) house a bumped semiconductor die, where interconnect terminals (interconnects) are formed on pads on the die. The process of forming the interconnects is often referred to as bumping. Typically, at the wafer level, the interconnects are formed from solder, such as, eutectic or high lead solder, on the pads of the constituent dies of the wafer. Alternatively, the interconnects can be made of metal such as gold, silver, tin and copper. In addition, the metal interconnects may also have a solder cap.
One method of forming CSPs is by molding the interconnect side of a bumped semiconductor wafer in mold compound. A bumped semiconductor wafer is placed on a contoured molding surface of a lower mold piece, with the interconnect side of the semiconductor wafer facing upwards i.e. with the interconnects extending upwardly. A predetermined amount of mold compound is then disposed on the interconnect side of the wafer. The lower mold piece and upper mold piece are then brought together, with the contoured molding surface and a flat molding surface on the upper mold piece forming a cavity with the substrate and the predetermined amount of mold compound enclosed in the cavity. As the lower mold piece and an upper mold piece are forced together under an imposed elevated temperature, the predetermined amount of mold compound is compressed to produce a predetermined pressure on the mold compound in the cavity.
The mold compound melts and the molten mold compound under the resultant mold compound pressure, flows across the interconnect side of the semiconductor wafer, and between the interconnects, to form a layer of mold compound on the interconnect side of the semiconductor wafer. After the mold compound has set, the upper and lower mold pieces are separated. Typically, the molded interconnect side of the semiconductor wafer adheres to the upper mold piece due to the binding force between the solidified mold compound and the flat molding surface of the upper mold piece.
Ideally, the predetermined amount of mold compound is selected such that there is a sufficient amount of mold compound to form a layer having a thickness that leaves the free ends of the interconnects exposed. However, when the predetermined amount of mold compound is used, a predetermined mold compound pressure may not be attained during compression between the mold pieces. Hence, this approach risks the formation of voids in the layer of molded compound on the semiconductor wafer.
Typically, to avoid the formation of voids, an excess amount of mold compound is employed to ensure the predetermined mold compound pressure is attained in the cavity during compression between the mold pieces. Consequently, the free ends of the interconnects are covered by the excess portion of the layer of mold compound that is formed. The excess portion is then removed by grinding it away to expose the free ends of the interconnects. However, due to the relatively large amount of mold compound that has to be removed, the grinding process is slow, adversely affecting throughput of CSP production. For example, the excess portion can be 20 microns (10−6 meters) thick, and the use of grinding, lapping, laser and/or plasma etching, or a combination of these, can take up to 30 minutes to remove the excess portion of mold compound.
Another disadvantage of this process, prior to grinding, is the difficulty in removing the molded semiconductor wafer from the upper mold piece without damaging and/or adversely affecting the constituent dies of the semiconductor wafer.
European patent application no. EP1035572 by Towa Corporation of Japan teaches a method of encapsulating a semiconductor wafer with mold compound that employs film disposed across the flat molding surface of the upper mold piece, prior to molding. Here, a semiconductor wafer having interconnects extending from the pads thereon, is placed in a cavity of a lower mold piece, with the interconnects extending upwardly, as before. A predetermined amount of mold compound is then disposed on the extending interconnects, and the film is disposed across the flat molding surface of the upper mold piece. The upper and lower mold pieces are then brought together under an imposed elevated temperature, compressing the predetermined amount of mold compound and the substrate in the cavity.
The molten mold compound flows across the surface of the interconnect side of the semiconductor wafer and between the interconnects to form a layer of mold compound on the semiconductor die. During compression, the free ends of the interconnects abut the film on the upper mold piece, where the film is intended to prevent the free ends of the interconnects from being covered with mold compound, thus avoiding the need for a subsequent grinding step. After the mold compound has set, the upper and lower mold pieces are separated and the film and molded semiconductor wafer adheres to the upper mold piece. Here the film allows the molded semiconductor wafer to be removed from the upper mold piece by pulling on it. Then, in a subsequent peeling step, the film is removed from the molded semiconductor wafer and discarded.
As mentioned earlier, the film is used to prevent the free ends of the interconnects from being covered in mold compound to avoid the need for grinding. In addition the film also allows the molded semiconductor wafer to be removed from the upper mold piece. However, a disadvantage of using film is that the film is discarded after each mold shot. Hence, the cost of using film is relatively high. Another disadvantage of using film is the need for the additional peeling step to remove the film from the molded semiconductor wafer. The peeling step has its cost, handling and throughput concerns. Yet another disadvantage of using film is that some of the mold compound can become trapped between the free ends of the interconnects and the film. Consequently, the additional step of removing the mold compound using the processes, such as grinding and etching, as mentioned earlier, may still need to be performed after the peeling step. A further disadvantage of using film is that air may become trapped between the film and the wafer, and this can lead to the formation of voids in the molded wafer, which can adversely affect the reliability of the constituent packaged semiconductor dies.
An alternative to using film to aid in the removal of the molded semiconductor wafer from the upper mold piece is to coat the flat molding surface of the upper mold piece with non-stick material such as Teflon®. While the layer of non-stick material assist in the removal of the molded semiconductor wafer from the upper mold piece, it does not ensure that the free ends of the interconnects are not covered by mold compound nor does the use of non-stick material have any effect on the amount of excess mold compound that has to be removed. Hence, the need for the subsequent steps of grinding or etching and the like, as described earlier. In addition, the layer of non-stick material has a relatively short useful life, and provisions will need to be made to replace the layer of non-stick material regularly.